`include "defines.v"
module ysyx_210448_clint (
  input wire clk,
  input rst,
  input wire [63:0] mtimecmp_data,
  input wire mtimecmp_open,
  input wire [63:0] mtime_data,
  input wire mtime_open,
  output reg [63:0] mcause_data,
  input wire [63:0] mstatus,
  input wire [63:0] mie,
  output reg [63:0] mtimecmp,
  output reg [63:0] mtime,
  output reg clock_interrupt
);

always @(posedge clk) 
	begin
		if (rst==1'b1) 
		begin
			mtime<=`ZERO_WORD;
			mtimecmp<=`ZERO_WORD;
		end
		else 
		begin
      mtime<=mtime+1;
			if (mtimecmp_open)
			begin
				mtimecmp<=mtimecmp_data;
			end
      if(mtime_open)
      begin
        mtime<=mtime_data;
      end
      else
      begin
        mtime<=mtime+1;
      end
		end
	end
always @(*) begin
  if(rst)
  begin
     mcause_data=`ZERO_WORD;
     clock_interrupt=1'b0;
  end
  else
  begin
     if((mtime>=mtimecmp)&&(mie[7]==1'b1)&&(mstatus[3]==1'b1))//时钟中断
     begin
      mcause_data=64'h8000000000000007;
      clock_interrupt=1'b1;
     end
     else
     begin
      clock_interrupt=1'b0;
      mcause_data=64'hb;
     end
  end
 end  


endmodule
